Hardware
- HardwarePost1 year ago @TheTuringPost
Graphcore IPU architecture and parallelism
Graphcore’s Intelligence Processing Unit has 1,472 processor cores, nearly 9,000 parallel threads, and 900 MB of In-Processor Memory. The post says it targets graph-based computation and irregular, sparse workloads.
The core count and on-chip memory architecture are relevant when evaluating accelerators for parallel workloads.
- HardwareArticle
GPU programming resources and an introduction to GPU systems
A collection of GPU programming resources includes a chapter explaining GPU chips, how they are networked, and implications for LLMs, with a focus on NVIDIA GPUs.
The chapter provides context on GPU architecture and interconnects that can help engineers reason about LLM workloads.
- HardwareArticle
Cornell Workshop Introduces GPU Architecture
Cornell’s GPU architecture workshop is suggested as a starting point for learning about GPUs. The post contrasts CPUs’ focus on complex control flow with GPUs’ throughput-oriented cores and shared memory.
A concise introduction can help engineers understand the architectural trade-offs behind GPU workloads.
- HardwareArticle
XIAOML Kit pairs ESP32-S3 sensors with an ML systems textbook
The XIAOML Kit includes a XIAO ESP32-S3 Sense board with a camera, digital microphone, and microSD slot, plus an expansion board with a 6-axis IMU and display. It complements a free machine learning systems textbook with kit lessons.
Engineers can use the kit and textbook to explore machine learning systems on embedded hardware.
- HardwareArticle
Ubiquiti Dream Router 7 review: WiFi 7 and 10GbE
StorageReview reviews the Dream Router 7, an all-in-one gateway combining WiFi 7, 10GbE, PoE, UniFi apps, and security tools for home and SMB use.
Engineers evaluating compact network gateways can compare its performance and features for UniFi deployments.
- HardwareArticle
An Open-Source, FPGA-Based 64-bit RISC-V Computer
The project aims to build a fully open-source computer system using an FPGA to implement a 64-bit RISC-V computer capable of running Linux and hosting its own development.
Engineers can explore changes to the CPU, memory hierarchy, instruction set, and software stack.
