{
  "markdown": "<!-- mcp-name: io.neosyn/cg-agent-kit -->\n\n# cg-agent-kit - an MCP server for FPGA design in C⏚\n\n[![ci](https://github.com/Neosyn-Logic/cg-agent-kit/actions/workflows/ci.yml/badge.svg)](https://github.com/Neosyn-Logic/cg-agent-kit/actions/workflows/ci.yml)\n[![License: MIT](https://img.shields.io/badge/License-MIT-yellow.svg)](https://opensource.org/licenses/MIT)\n\nGive an AI agent the ability to design real hardware. `cg-agent-kit` is a\n[Model Context Protocol](https://modelcontextprotocol.io) server that drives the\nopen-source **C⏚ Verilog compiler** - so an agent writes a C-like HDL, and the\nserver compiles, checks, generates Verilog, and synthesis-checks it against the\n*real* toolchain instead of hallucinating Verilog that doesn't build.\n\nC⏚ (\"C-Ground\") is a hardware description language with C-like syntax that\ncompiles to clean, standard Verilog. The compiler is open source at\n**[github.com/Neosyn-Logic/cg-compiler](https://github.com/Neosyn-Logic/cg-compiler)**.\n\n## Tools\n\n| Tool | What it does |\n|------|--------------|\n| `cg_check` | Compile + validate C⏚; structured diagnostics (file:line, the fix) |\n| `cg_generate_verilog` | Emit synthesizable Verilog |\n| `cg_simulate` | Simulate a design (`iverilog` backend, or the commercial fast sim) |\n| `cg_synth` | Yosys-synthesize the Verilog: REAL / FOLDED / SUSPECT verdict + cell count |\n| `cg_example` | Scored lookup into a curated, **validated-code dictionary** (28 entries) |\n| `cg_suggest_for_error` | Map a compiler error to the recipe with the fix pattern |\n| `cg_fsm` / `cg_graph` | A task's compiled state machine / a network's graph |\n| `cg_docs` | C⏚ language + patterns reference |\n\nThe kit's organizing idea: agents **seed-and-adapt** from validated code and\n**verify against the real compiler** at every step - not invent-from-scratch.\n\n## Open vs commercial\n\nThis kit and the compiler it drives are open. The **fast (bytecode) cycle-accurate\nsimulator** is part of the commercial Neosyn SDK - so `cg_simulate`'s default\n`bytecode` backend asks you to upgrade, while the **`iverilog` backend works\nfully** (generate Verilog + run Icarus Verilog). Everything else -\ncheck, generate, synth, the dictionary, docs - runs entirely on the open compiler.\nMore at [neosyn.io/open](https://neosyn.io/open).\n\n## Install\n\n```bash\npip install cg-agent-kit\n```\n\nThen point it at a built C⏚ compiler jar (download the prebuilt jar from\n[cg-compiler releases](https://github.com/Neosyn-Logic/cg-compiler/releases/latest),\nor build from source):\n\n```bash\nexport CG_JAR=/path/to/cg-language-server.jar\n```\n\n(Optional, for `cg_synth` and the `iverilog` sim backend, install `yosys` and\n`iverilog`.)\n\n## Run\n\nAs an MCP server (for Claude Desktop, Cursor, Windsurf, or any MCP client):\n\n```bash\ncg-mcp-server\n```\n\nAdd it to your MCP client config, e.g.:\n\n```json\n{\n  \"mcpServers\": {\n    \"cg\": { \"command\": \"cg-mcp-server\", \"env\": { \"CG_JAR\": \"/path/to/cg-language-server.jar\" } }\n  }\n}\n```\n\nOr call the verification functions directly from Python:\n\n```python\nfrom cg_agent_kit import cg_mcp_server as cg\nprint(cg.check(open(\"Counter.cg\").read()))\nprint(cg.generate(open(\"Counter.cg\").read()))\n```\n\nThe kit bundles 28 validated C⏚ designs and the language + CPU-pattern\nreferences the `cg_docs` tool serves.\n\n## License\n\nMIT - see [LICENSE](LICENSE). C⏚ began as the Synflow Cx toolchain.\n",
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  "repo_slug": "neosyn-logic/cg-agent-kit",
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  "api": "https://agentalog.com/api/listings/mcp_io_neosyn_cg_agent_kit_a930f2c7/readme"
}